Image reading device

ABSTRACT

An image reading device ready to operate at higher speed is built as an IC chip having a plurality of processing sections, of which each has a plurality of image reading photoelectric conversion elements, a plurality of transistors for reading a photoelectric conversion signal from the image reading photoelectric conversion elements, a signal selection circuit for sequentially selecting the plurality of transistors, and a signal output line by way of which the photoelectric conversion signal is transmitted.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to an image reading device, such asan image sensor, that converts optical information to an electricsignal.

[0003] 2. Description of the Prior Art

[0004] As FIG. 3 shows, an image reading device is composed of IC chipsK₁, K₂, . . . , K_(m), for reading an image, arranged in a row andmounted on a printed circuit board (not shown). The IC chips K₁, K₂, . .. , K_(m) sequentially output photoelectric conversion signals, whichare then converted by an A/D converter 100 into a digital signal, whichis then fed out via an output terminal 200. The IC chips K₁, K₂, . . . ,K_(m) all have the same circuit configuration, of which a conventionalexample will be described below with reference to FIG. 4.

[0005] Photodiodes PD₁, PD₂, . . . , PD_(n), serving as photoelectricconversion elements, have their anodes connected to ground, and havetheir cathodes connected respectively to the gates of p-channel MOSFETs(metal-oxide semiconductor field-effect transistors) A₁, A₂, . . . ,A_(n) for amplification. The transistors A₁, A₂, . . . , A_(n) receive,at their sources, constant currents respectively from constant-currentsources I₁, I₂, . . . , I_(n), and have their drains connected toground.

[0006] A bias voltage supply circuit 2 outputs a positive direct-currentvoltage stably. The voltage (hereinafter referred to as the “biasvoltage”) output from the bias voltage supply circuit 2 is applied,through the drain-source channels of p-channel MOSFETs B₁, B₂, . . .B_(n) for switching, to the cathodes of the photodiodes PD₁, PD₂, . . ., PD_(n) respectively.

[0007] In this circuit configuration, when the transistor B_(x). (x=1,2, . . . , n) remains on for a predetermined time or longer, a reversebias is applied to the photodiode PD_(x), and thus a predeterminedamount of electric charge is accumulated therein. In the followingdescriptions, this will be depicted as “the photodiode PD_(x) beinginitialized.”

[0008] When the transistor B_(x) turns from on to off, theinitialization of the photodiode PD_(x) is broken off, and theaccumulated electric charge is discharged in proportion to the amount ofincident light, causing a current to flow. Thus, the photodiode PD_(x)gives a voltage proportional to the amount of incident light.

[0009] Moreover, a transistor C_(x) turns on, with the result that thevoltage signal (hereinafter referred to simply as “the signal of thephotodiode PD_(x)”) at the cathode of the photodiode PD_(x) is amplifiedby a source-follower circuit formed by the transistor A_(x), is thensubjected to further amplification, waveform shaping, and otherprocessing by an output circuit 51, and is then fed out via a terminalT_(OUT) (hereinafter, this will be depicted as “the signal of thephotodiode PD_(x) being read out”).

[0010] A control circuit 52 controls the transistors C_(x) in such a waythat the signals of the photodiodes PD₁, PD₂, . . . , PD_(n) are outputsequentially, and also controls the transistors Bx in such a way thatthe photodiode PD_(x) is initialized every time the signal of thisphotodiode PD₁ is read out.

[0011] However, in this conventional circuit configuration, the signalsof all the photodiodes PD₁, PD₂, . . . , PD_(n) are transmitted to theoutput circuit 51 by way of a single output line L, which is thusprovided so as to be common to as many as several tens to severalhundred photodiodes. This makes the output line L considerably long, andthus imposes a limit on the operating frequency of the image readingdevice, because, the longer the conductor laid as the output line L, thehigher its resistance and capacitance, and thus the greater theresulting time constant.

[0012] Moreover, in the conventional circuit configuration, there arevariations in the characteristics of the individual photodiodes PD₁,PD₂, . . . , PD_(n), but nevertheless the signals read out from them arefed out intact. As a result, according to the position of thephotodiodes within the IC chip, for example, the characteristics of thesemiconductors, such as their degree of impurity and thickness, and thelight shield conditions for the individual photodiodes vary, and thusthe signals that these photodiodes output vary.

SUMMARY OF THE INVENTION

[0013] An object of the present invention is to provide an image readingdevice that is ready to operate at a higher operating frequency.

[0014] To achieve the above object, according to the present invention,an image reading device is built as an IC chip having a plurality ofprocessing sections, of which each has a plurality of image readingphotoelectric conversion elements, a plurality of transistors forreading a photoelectric conversion signal from the image readingphotoelectric conversion elements, a signal selection circuit forsequentially selecting the plurality of transistors, and a signal outputline by way of which the photoelectric conversion signal is transmitted.

[0015] This arrangement helps shorten the signal output line within eachprocessing section. As a result, it is possible to reduce the resistanceand capacitance of the conductor laid as the signal output line.Moreover, it is possible to reduce the number of transistors that areconnected to a single signal output line and thereby reduce theparasitic capacitance connected to a single signal output line. Thismakes it possible to increase the operation speed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] This and other objects and features of the present invention willbecome clear from the following description, taken in conjunction withthe preferred embodiments with reference to the accompanying drawings inwhich:

[0017]FIG. 1 is a diagram showing the circuit configuration of each ofthe IC chips constituting an image reading device embodying theinvention;

[0018]FIG. 2 is a timing chart of the relevant signals in each of the ICchips constituting the image reading device embodying the invention;

[0019]FIG. 3 is a diagram showing an outline of the circuitconfiguration of an image reading device; and

[0020]FIG. 4 is a diagram showing the circuit configuration of each ofthe IC chips constituting a conventional image reading device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, an embodiment of the present invention will bedescribed with reference to the drawings. First, the circuitconfiguration of each of the IC chips constituting an image readingdevice embodying the invention will be described with reference to FIG.1.

[0022] Photodiodes PD₁, . . . , PD_(n), PD₁′, . . . , PD_(n)′, servingas photoelectric conversion elements, have their anodes connected toground, and have their cathodes connected respectively to the gates ofp-channel MOSFETs A₁, . . . , A_(n), A₁′, . . . , A_(n)′ foramplification.

[0023] Here, the photodiodes PD₁′, . . . , PD_(n)′ are shielded fromlight so as not to be involved in image reading. In the followingdescriptions, these photodiodes will be referred to also as the “dummyphotodiodes.” On the other hand, the photodiodes PD₁, . . . , PD_(n) arenot shielded from light, and are used in image reading. In the followingdescriptions, these photodiodes will be referred to also as the “imagereading photodiodes.”

[0024] The transistors A₁, . . . , A_(n), A₁′, . . . , A_(n)′ have theirsources connected, through the drain-source channels of p-channelMOSFETs D₁, . . . , D_(n), D₁′, . . . , D_(n)′ respectively, to a supplyvoltage. The transistors D₁, . . . , D_(n), D₁′, . . . , D_(n)′ havetheir gates connected to ground, and the transistors A₁, . . . , A_(n),A₁′, . . . , A_(n)′ receive constant currents at their sources.

[0025] The transistors A₁, . . . , A_(n), A₁′, . . . , A_(n)′ have theirdrains connected, through the drain-source channels of n-channel MOSFETsE₁, . . . , E_(n), E₁′, . . . , E_(n)′ respectively, to ground. A logiccircuit 1 controls the transistors E₁, . . . , E_(n), E₁′, . . . ,E_(n)′ in such a way that they remain on only from immediately beforethe start of the reading of the signal from the first image readingphotodiode PD₁ until the completion of the reading of the signal fromthe last image reading photodiode PD_(n). This helps reduce electricpower consumption.

[0026] A bias voltage (i.e. a stable direct-current voltage output froma bias voltage supply circuit 2) is applied, through the drain-sourcechannels of p-channel MOSFETs B₁, . . . , B_(n), B₁′, . . . , B_(n)′ forswitching, to the cathodes of the photodiodes PD₁, . . . , PD_(n), PD₁′,. . . , PD_(n)′ respectively. The transistors B₁, . . . , B_(n), B₁′, .. . , B_(n)′, respectively receive, at their gates, signals output fromterminals M₁, . . . , M_(n), M₁′, . . . , M_(n)′ of a shift register 3.

[0027] The transistors A₁, . . . , A_(k) have their sources connected,respectively through the drain-source channels of p-channel MOSFETs C₁,. . . , C_(k) for switching, together to a first output line L1. Thetransistors A_(k+1), . . . , A_(n) have their sources connected,respectively through the drain-source channels of p-channel MOSFETsC_(k+1), . . . , C_(n) for switching, together to a second output lineL2. The first and second output lines L1 and L2 are connected,respectively through a first and a second output line switching switchS1 and S2, together to the gate of an n-channel MOSFET 4-1.

[0028] The transistors A₁′, . . . , A_(k)′ have their sources connected,respectively through the drain-source channels of p-channel MOSFETs C₁′,. . . , C_(k)′ for switching, together to a third output line L3. Thetransistors A_(k+1)′, . . . , A_(n)′ have their sources connected,respectively through the drain-source channels of p-channel MOSFETsC_(k+1)′, . . . , C_(n)′ for switching, together to a fourth output lineL4. The third and fourth output lines L3 and L4 are connected,respectively through a third and a fourth output line switching switchS3 and S4, together to the gate of an n-channel MOSFET 4-2.

[0029] The first, second, third, and fourth output line switchingswitches S1, S2, S3, and S4 are each composed of, for example, ap-channel MOSFET, and their on/off states are controlled by the logiccircuit 1 in the manner described later.

[0030] The transistors C₁, . . . , C_(n), C₁′, . . . , C_(n)′respectively receive, at their gates, signals output from terminals O₁,. . . , O_(n), O₁′, . . . , O_(n)′ of the shift register 3. The sourcesof the transistors 4-1 and 4-2 are connected, through constant currentsources 5-1 and 5-2 respectively, to ground. The drains of thetransistors 4-1 and 4-2 are connected to the supply voltage.

[0031] Buffer amplifiers 6-1 and 6-2 are each composed of an operationalamplifier having its output fed back to its own inverting input terminal(−). The input sides of the buffer amplifiers 6-1 and 6-2 (i.e. thenon-inverting input terminal (+) of each operational amplifier) areconnected to the sources of the transistors 4-1 and 4-2 respectively.

[0032] That is, the signals of the image reading photodiodes PD_(x)(x=1, 2, . . . , n) are fed, through the source follower circuits formedby the transistors A_(x) respectively, and then through the sourcefollower circuit formed by the transistor 4-1, to the buffer amplifier6-1. On the other hand, the signals of the dummy photodiodes PD_(x)′ arefed, through the source follower circuits formed by the transistorsA_(x)′ respectively, and then through the source follower circuit formedby the transistor 4-2, to the buffer amplifier 6-2.

[0033] The output side (the output terminal of the operationalamplifier) of the buffer amplifier 6-1 is connected through a resistorR₁ to the inverting input terminal (−) of an operational amplifier 7.The output side of the buffer amplifier 6-2 is connected through aresistor R₂ to the non-inverting input terminal (+) of the operationalamplifier 7.

[0034] To the non-inverting input terminal (+) of the operationalamplifier 7, a direct-current reference voltage is fed from outside theIC chip via a terminal T_(REF) thereof through a resistor R₃. The outputterminal of the operational amplifier 7 is connected through a resistorR₄ to its own inverting input terminal (−), and also to thenon-inverting input terminal (+) of an operational amplifier 8.

[0035] To the inverting input terminal (−) of the operational amplifier8, its own output terminal is connected through a resistor R₅, and alsothe reference voltage fed from outside via the terminal T_(REF) isapplied through a resistor R₆.

[0036] A buffer amplifier 9 is composed of an operational amplifier withits output fed back to its own inverting input terminal (−). To theinput side of the buffer amplifier 9, the output terminal of theoperational amplifier 8 is connected through a capacitor 10. Moreover,the input side of the buffer amplifier 9 is connected through a switch11 to the node between resistors R₇ and R₈ that are connected in seriesbetween the terminal T_(REF), to which the reference voltage is appliedfrom outside, and ground.

[0037] The switch 11 is composed of, for example, an analog switch, andis controlled by the logic circuit 1 in such a way as to remain on onlyfor a predetermined time before the start of the reading of the firstimage reading photodiode PD₁.

[0038] The output of the buffer amplifier 9 is fed out through a switch12 via a terminal T_(OUT) of the IC chip. The switch 12 is composed of,for example, an analog switch, and is controlled by the logic circuit 1in such a way as to remain on only from immediately before the start ofthe reading of the signal from the first image reading photodiode PD₁until the completion of the reading of the signal from the last imagereading photodiode PD_(n).

[0039] The logic circuit 1 receives a clock signal CLK fed in fromoutside via a terminal T_(CLK) of the IC chip and a start trigger signalST fed in from outside via a terminal T_(SI) of the IC chip. The clocksignal CLK fed to the individual IC chips are common to all of them. Onthe basis of the clock signal CLK and the start trigger signal ST fedthereto, the logic circuit 1 controls the transistors E_(x) and theswitches 11 and 12 in the manner described above.

[0040] Moreover, before the start of the reading of the signal from thefirst image reading photodiode PD₁, i.e. before time point t₃ shown inFIG. 2 described later, the logic circuit 1 turns on the first outputline switching switch S1, turns off the second output line switchingswitch S2, turns on the third output line switching switch S3, and turnsoff the fourth output line switching switch S4. Furthermore, in the lasthalf of the period in which the signal from the photodiode PD_(k) isread, i.e. between time points t_(2k+2) and t_(2k+3) shown in FIG. 2described later, the logic circuit 1 turns off the first output lineswitching switch S1, turns on the second output line switching switchS2, turns off the third output line switching switch S3, and turns onthe fourth output line switching switch S4.

[0041] The start trigger signal ST, fed in via the terminal T_(SI) ofthe IC chip, and the clock signal CLK, fed in via the terminal T_(CLK)of the IC chip, are also fed through the logic circuit 1 to the shiftregister 3. As FIG. 2 shows, the shift register 3 sequentially outputs,in synchronism with the second and following trailing edges of the clocksignal CLK after the rising edge of the start trigger signal ST,negative pulses, each having a pulse width equal to one period of theclock signal CLK, via its terminals O₁, O₂, . . . . O_(n). The shiftregister 3 outputs the same signals as it outputs via its terminals O₁,O₁, . . . , O_(n) also via its terminals O₁′, O₂′, . . . , O_(n)′.

[0042] As a result, the transistors C₁ and C₁′, the transistors C₂ andC₂′, . . . , the transistors C_(n) and C_(n)′ are sequentially kept onfor one period of the clock signal CLK one pair after another,specifically in such a way that the transistors C₁ and C₁′ remain onbetween time points t₃ and t₅, the transistors C₂ and C₂′ remain onbetween time points t₅ and t₇, and so forth. Thus, the signals of theimage reading photodiodes PD₁, PD₂, . . . , PD_(n) are sequentially fedto the gate of the transistor 4-1, and the signals of the dummyphotodiodes PD₁′, PD₂′, . . . , PD_(n)′ are sequentially fed to the gateof the transistor 4-2.

[0043] Moreover, as FIG. 2 shows, the shift register 3 also sequentiallyoutputs, in synchronism with the third and following rising edges of theclock signal CLK after the rising edge of the start trigger signal ST,negative pulses, each having a pulse width equal to one period of theclock signal CLK, via its terminals M₁, M₂, . . . , M_(n).

[0044] As a result, the transistors B₁, B₂, . . . , B_(n) aresequentially kept on for one period of the clock signal CLK one afteranother, specifically in such a way that the transistor B₁ remains onbetween time points t₄ and t₆, the transistor B₂ remains on between timepoints t₆ and t₈, and so forth. Thus, the image reading photodiodes PD₁,PD₂, . . . , PD_(n) are initialized sequentially.

[0045] In this way, if one pays attention to the first image readingphotodiode PD₁, whereas the transistor C₁ is kept on between time pointst₃ and t₅ so that the signal of the photodiode PD₁ is read out, thetransistor B₁ is also kept on between time points t₄ and t₅ (i.e. duringthe last half of the read period) so that the photodiode PD₁ isinitialized. Thus, only the signal read out between time points t₃ andt₄ (i.e. during the first half of the read period) is actually used.Likewise, also with the other image reading photodiodes PD₂, PD₃, . . ., PD_(n), only the signals read out during the first half of theirrespective read period are actually used.

[0046] Moreover, as FIG. 2 shows, the shift register 3 also sequentiallyoutputs, in synchronism with the trailing edges of the clock signal CLKafter the rising edge of the start trigger signal ST, negative pulses,each having a pulse width equal to one period of the clock signal CLK,via its terminals M₁′, M₂′, . . . , M_(n)′.

[0047] As a result, the transistors B₁′, B₂′, . . . , B_(n)′ aresequentially kept on for one period of the clock signal CLK one afteranother, specifically in such a way that the transistor B₁′ remains onbetween time points t₁ and t₃, the transistor B₂′ remains on betweentime points t₃ and t₅, and so forth. Thus, the dummy photodiodes PD₁′,PD₂′, . . . , PD_(n)′ are initialized sequentially.

[0048] Moreover, the shift register 3 outputs, at its terminal E, asignal, which is fed out of the IC chip via its terminal T_(SO) so as tobe fed to the terminal T_(SI) of the next IC chip. That is, this signalis used as the start trigger signal ST in the next IC chip. Here, theshift register 3 outputs one positive pulse via its terminal E with suchappropriate timing as to prevent interference between the reading of thesignal of the last image reading photodiode PD_(n) of the IC chip underdiscussion and the reading of the signal of the first image readingphotodiode PD₁ of the next IC chip.

[0049] In this circuit configuration, the differences between thesignals of the image reading photodiodes PD_(x) and the signals of thecorresponding dummy photodiodes PD_(x)′ are output. Thus, even if thereare variations among the output signals from the individual photodiodeswithin an IC chip according to their position, for example, due tovariations in the characteristics of the semiconductors, such as theirdegree of impurity and thickness, and variations in the light shieldconditions of the individual photodiodes, such variations are cancelled.This helps enhance the uniformity of the signal levels obtained.

[0050] Moreover, instead of transmitting all the signals from theindividual image reading photodiodes PD₁, . . . , PD_(n) to the outputcircuit H by way of a single output line, the signals from the group ofthe image reading photodiode PD₁, . . . , PD_(k) are transmitted by wayof the first output line L1, and the signals from the group of the imagereading photodiode PD_(k+1), . . . , PD_(n) are transmitted by way ofthe first output line L2. Likewise, instead of transmitting all thesignals from the dummy photodiodes PD₁′, . . . , PD_(n)′ to the outputcircuit H by way of a single output line, the signals from the group ofthe dummy photodiode PD₁′, . . . , PD_(k)′ are transmitted by way of thethird output line L3, and the signals from the group of the dummyphotodiode PD_(k+1)′, . . . , PD_(n)′ are transmitted by way of thefourth output line L4. This makes it possible to shorten the output linesubstantially in half. Shortening the conductor laid as the output lineresults in reducing its resistance and capacitance, and also in reducingthe parasitic capacitance due to the transistors connected thereto inhalf. This reduces the resulting time constant, and thus makes itpossible to increase the operating frequency of the image readingdevice. Specifically, whereas the operating frequency conventionallyachieved is limited to 1.5 to 2.0 MHz, that achieved in this embodimentis as high as 3.0 to 4.0 MHz.

[0051] Where, as in the embodiment described above, the image readingphotodiodes are divided into two groups, they are classified, forexample, according to whether the signals from them are read out in thefirst half or latter half of the period for reading one complete image.The image reading photodiodes may be divided into a plurality of groups,i.e. not only two but also three or more; in any case, output lines areprovided one for each group.

[0052] It is possible to omit the dummy photodiodes completely, orprovide only one dummy photodiode common to all the image readingphotodiodes and output the differences between the signals of theindividual image reading photodiodes and the signal of the dummyphotodiode. This helps simplify the circuit configuration, and thuscontributes to miniaturization and cost reduction.

[0053] Providing as many dummy photodiodes as image reading photodiodes,however, makes it possible to arrange the dummy photodiodes close to thecorresponding image reading photodiodes. Thus, in this arrangement,outputting the differences between the signals of the image readingphotodiodes and the signals of the dummy photodiodes arranged closethereto makes it possible to reduce variations among the output signalsfrom the individual photodiodes within an IC chip according to theirposition, for example, due to variations in the characteristics of thesemiconductors, such as their degree of impurity and thickness, andvariations in the light shield conditions of the individual photodiodes.

[0054] As described above, according to the present invention, in animage reading device, it is possible to shorten the output line by wayof which signals obtained from photoelectric conversion elements aretransmitted to an output circuit, and also reduce the number oftransistors connected to one output line. That is, it is possible toreduce the resistance and capacitance of the conductor laid as theoutput line. This reduces the parasitic capacitance due to thetransistors connected to the output line, and thereby reduces theresulting time constant. In this way, it is possible to increase theoperating frequency of the image reading device and obtain outputscorrected for variations in the characteristics of photodiodes.

What is claimed is:
 1. An IC chip for reading an image, comprising: aplurality of image reading photoelectric conversion elements a pluralityof first transistors for reading a first photoelectric conversion signalfrom the image reading photoelectric conversion elements; a first signalselection circuit for sequentially selecting the plurality of firsttransistors; a plurality of dummy photoelectric conversion elementsarranged respectively near the image reading photoelectric conversionelements and shielded from light; a plurality of second transistors forreading a second photoelectric conversion signal from the dummyphotoelectric conversion elements; a second signal selection circuit forsequentially selecting the plurality of second transistors; and anoutput circuit for processing the first and second photoelectricconversion signals and then outputting a resulting signal, wherein theoutput circuit outputs a difference between the first and secondphotoelectric conversion signals to correct the first photoelectricconversion signal.
 2. An IC chip for reading an image, comprising: aplurality of first processing sections, each comprising: a plurality ofimage reading photoelectric conversion elements; a plurality of firsttransistors for reading a first photoelectric conversion signal from theimage reading photoelectric conversion elements; a first signalselection circuit for sequentially selecting the plurality of firsttransistors; and a first signal output line by way of which the firstphotoelectric conversion signal is transmitted, wherein provision of theplurality of first processing sections reduces a total resistance and atotal capacitance of the first signal output lines provided within thefirst processing sections, reduces a total parasitic capacitance of thefirst transistors connected to the first signal output lines, andthereby permits the image reading device to operate at a higheroperation speed.
 3. An IC chip for reading an image as claimed in claim2, further comprising: a dummy photoelectric conversion element shieldedfrom light; and an output circuit for outputting a difference betweenthe first photoelectric conversion signal and a second photoelectricconversion signal read from the dummy photoelectric conversion element,wherein the output circuit corrects the first photoelectric conversionsignal.
 4. An IC chip for reading an image, comprising: a plurality offirst processing sections, each comprising: a plurality of image readingphotoelectric conversion elements; a plurality of first transistors forreading a first photoelectric conversion signal from the image readingphotoelectric conversion elements; a first signal selection circuit forsequentially selecting the plurality of first transistors; and a firstsignal output line by way of which the first photoelectric conversionsignal is transmitted; a plurality of second processing sectionsprovided so as to pair respectively with the first processing sections,the second processing sections each comprising: a plurality of dummyphotoelectric conversion elements arranged respectively near the imagereading photoelectric conversion elements and shielded from light; aplurality of second transistors for reading a second photoelectricconversion signal from the dummy photoelectric conversion elements; asecond signal selection circuit for sequentially selecting the pluralityof second transistors; and a second signal output line by way of whichthe second photoelectric conversion signal is transmitted; an outputcircuit for processing the first and second photoelectric conversionsignals and then outputting a resulting signal; and a signal output lineswitching circuit for selecting the first and second signal output linesand connecting the selected first and second signal output lines to theoutput circuit, wherein the output circuit outputs a difference betweenthe first and second photoelectric conversion signals to correct thefirst photoelectric conversion signal.
 5. An image reading devicecomprising: one or more IC chips, each comprising: a plurality of imagereading photoelectric conversion elements; a plurality of firsttransistors for reading a first photoelectric conversion signal from theimage reading photoelectric conversion elements; a first signalselection circuit for sequentially selecting the plurality of firsttransistors; a plurality of dummy photoelectric conversion elementsarranged respectively near the image reading photoelectric conversionelements and shielded from light; a plurality of second transistors forreading a second photoelectric conversion signal from the dummyphotoelectric conversion elements; a second signal selection circuit forsequentially selecting the plurality of second transistors; an outputcircuit for outputting a difference between the first and secondphotoelectric conversion signals as a corrected first photoelectricconversion signal; a trigger signal input terminal by way of which asignal for sequentially scanning an image being read is fed in from anIC chip in a previous stage; a trigger signal output terminal by way ofwhich a signal for sequentially scanning the image being read is fed outto an IC chip in a following stage; a clock input terminal by way ofwhich a clock is fed in; and a reference voltage input terminal by wayof which a reference voltage for the output circuit is fed in; and anA/D converter for converting a signal output from the output circuitinto a digital signal, wherein said one or more IC chips each startscanning the image being read on receiving an input signal at thetrigger input terminal thereof, and, on completion of the scanning,outputs, at the trigger output terminal thereof, a signal for continuingsequential scanning to the IC chip in the following stage.
 6. An imagereading device comprising: one or more IC chips, each comprising: aplurality of processing sections, each comprising: a plurality of imagereading photoelectric conversion elements; a plurality of transistorsfor reading a photoelectric conversion signal from the image readingphotoelectric conversion elements; a signal selection circuit forsequentially selecting the plurality of transistors; a signal outputline by way of which the photoelectric conversion signal is transmitted;a trigger signal input terminal by way of which a signal forsequentially scanning an image being read is fed in from an IC chip in aprevious stage; a trigger signal output terminal by way of which asignal for sequentially scanning the image being read is fed out to anIC chip in a following stage; and a clock input terminal by way of whicha clock is fed in; wherein said one or more IC chips each start scanningthe image being read on receiving an input signal at the trigger inputterminal thereof, and, on completion of the scanning, outputs, at thetrigger output terminal thereof, a signal for continuing sequentialscanning to the IC chip in the following stage.
 7. An image readingdevice as claimed in claim 6, wherein the IC chips each furthercomprise: a dummy photoelectric conversion element shielded from light;an output circuit for outputting a difference between the photoelectricconversion signal and a signal read from the dummy photoelectricconversion element, wherein the output circuit corrects thephotoelectric conversion signal.
 8. An image reading device comprising:one or more IC chips, each comprising: a plurality of first processingsections, each comprising: a plurality of image reading photoelectricconversion elements; a plurality of first transistors for reading afirst photoelectric conversion signal from the image readingphotoelectric conversion elements; a first signal selection circuit forsequentially selecting the plurality of first transistors; and a firstsignal output line by way of which the first photoelectric conversionsignal is transmitted; a plurality of second processing sectionsprovided so as to pair respectively with the first processing sections,the second processing sections each comprising: a plurality of dummyphotoelectric conversion elements arranged respectively near the imagereading photoelectric conversion elements and shielded from light; aplurality of second transistors for reading a second photoelectricconversion signal from the dummy photoelectric conversion elements; asecond signal selection circuit for sequentially selecting the pluralityof second transistors; and a second signal output line by way of whichthe second photoelectric conversion signal is transmitted; an outputcircuit for outputting a difference between the first and secondphotoelectric conversion signals as a corrected first photoelectricconversion signal; a signal output line switching circuit for selectingthe first and second signal output lines and connecting the selectedfirst and second signal output lines to the output circuit; a triggersignal input terminal by way of which a signal for sequentially scanningan image being read is fed in from an IC chip in a previous stage; atrigger signal output terminal by way of which a signal for sequentiallyscanning the image being read is fed out to an IC chip in a followingstage; and a clock input terminal by way of which a clock is fed in; anA/D converter for converting a signal output from the output circuitinto a digital signal, wherein said one or more IC chips each startscanning the image being read on receiving an input signal at thetrigger input terminal thereof, and, on completion of the scanning,outputs, at the trigger output terminal thereof, a signal for continuingsequential scanning to the IC chip in the following stage.